Building a design with FuseSoC

The FuseSoC build system pieces together a hardware design from individual cores.

Building a design in FuseSoC means calling a tool flow to produce some output, and execute it. Depending on the target and the tool flow chosen, the build process can do and produce very different things: it could produce a runnable simulation, generate an FPGA bitstream, or run a static analysis tool to check for common programming errors.

Two steps are required to build a hardware design with FuseSoC:

  1. Write one or more FuseSoC core description files. See Writing core files for information on how to write core description files.

  2. Call fusesoc run. FuseSoC is a command-line tool and accessible through the fusesoc command. See Running FuseSoC for information on how to use the fusesoc command.

Typically, FuseSoC support can be added to an existing design without changes to the directory structure or the source files.

The first three sections are recommended reading for all users of FuseSoC. The first section Writing core files is an introduction into core description files and how to write them. The second and third section, Interfacing EDA tool flows and Dependencies: link cores together for re-use look at how to customize what the (EDA) tools are doing, and how cores can be combined to form a larger system.

The subsequent sections are advanced topics, which are only relevant in some projects.

A full reference documentation on the CAPI2 core file format can be found in the section ref_capi2.

In this section